HIP6502B

The HIP6502B complements either an HIP6020 or an IP6021 in ACPI-compliant designs for microprocessor and omputer applications. The HIP6502B IC ntegrates four linear ontrollers/regulators, switching, monitoring and control unctions into a 20-pin SOIC package. One linear controller enerates the 3.3V_DUAL /3.3V_SB voltage plane from the ATX supply's 5VSB output, powering the south bridge and the PCI slots through an external pass transistor during sleep states (S3, S4/S5). A second transistor is used to switch in the ATX 3.3V output for operation during S0 and S1/S2 (active) operating states. Two linear controllers/regulators supply at choice either or both of the computer system's 2.5V or 3.3V memory power through external pass transistors in active states.

During sleep states, integrated pass transistors supply the sleep power for HIP6502B. Another controller powers up the 5V_DUAL  plane by switching in the ATX 5V output in active states, and the ATX 5VSB in sleep states. One internal regulator outputs a dedicated, noise-free 2.5V clock chip supply. The HIP6502B's operating mode (active outputs or sleep outputs) is selectable through two digital control pins, S3 and S5. Enabling sleep state support on the 5V_DUAL  output is offered through the EN5VDL pin. In active state, the 3.3V_DUAL  and 3.3V_MEM linear regulators use external N-channel pass MOSFETs to connect the outputs directly to the 3.3V input supplied by an ATX (or equivalent) power supply, for minimal losses. In sleep state, power delivery on both outputs is transferred to NPN transistors -external to the controller on the 3.3V_DUAL , internal on the 3.3V_MEM . Active state regulation on the 2.5V_MEM   output is performed through an external NPN transistor. In sleep state, conduction on this output is transferred to an internal pass transistor. The 5V_DUAL  output is powered through two external MOS transistors. In sleep states, a PMOS (or PNP) transistor conducts the current from the ATX 5VSB output; while in active state, current flow is transferred to an NMOS transistor connected to the ATX 5V output. The operation of the 5V_DUALoutput is dictated not only by the status of the S3 and S5 pins, but that of the EN5VDL pin as well. The 3.3V_DUAL /3.3V_SB  output is active for as long as the ATX  5VSB voltage is applied to the chip. The 2.5V_CLK  output is only active during S0 and S1/S2, and uses the 3V3 pin as input source for its internal pass element.