HI3197

Features:

• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits
• Conversion Rate 125 MSPS (PECL) 100 MSPS (TTL)
• Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL
• Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ)
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pV•s
• Clock, Reset Input Level: TTL and PECL Compatible 2:1 Multiplexed Input Function
• 1/2 Frequency-Divided Clock Output Possible by the Built- In Clock Frequency Divider Circuit
• Voltage Output (50Ω Load Drive Possible)
• Single Power Supply or ±Dual Power Supplies
• Polarity Switching Function of Reset Signal


Application

• LCD
• DDS
• HDTV
• Communications (QPSK, QAM)


Pinout




Specifications

Supply Voltage (AV_CC0, AV_CC2, DV_CC2) . . . . . . . . . . . -0.5 to +7.0V
AGND2, DGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . -7.0 to +0.5V
DV_CC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..  . -0.5 to +7.0V
AV_CC2 - AGND2. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . -0.5 to +7.0V
AV_CC0 - AGND2. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . -0.5 to +7.0V
DV_CC2 - DGND2 . . . . . . . . . . . . . . . . . . . . . . . . .. . . . -0.5 to +7.0V
Input Voltage
VSET, . . . . . . . . . . . . . . . . . . . . . . . .. .AGND2 -05 to AV_CC2 + 0.5V
TTL Pin . . . . . . . . . . . . . . . . . . . . .. . . DGND1 -0.5 to DV_CC1 + 0.5V
PECL Pin, . . . . . . . . . . . . . . . . . .. . . . DGND1 -0.5 to DV_CC1 + 0.5V
PS. . . . . . . . . . . . . . . . . . . . . . . . . . . DGND1 -0.5 to DV_CC1 + 0.5V
(Others), VOCLP . . . . . . . . . . . . . . . . . DGND1 -0.5 to DV_CC1 + 5V


Description

The HI3197 is a high-speed D/A converter which can perform the multiplexed input of the two system 10-bit data.

The maximum conversion rate of HI3197 achieves 125 MSPS. The multiplexed operation is possible by the 1/2 frequencydivided clock or by halving the frequency of the clock with the clock frequency divider circuit having the reset pin in the IC. The data input is TTL; the clock input pin and reset input pin can select either TTL or PECL according to the application.