Features: ·Automatic conversion of serial ARINC 429, 575 & 561 data to 16-bit parallel data·High speed parallel 16-bit data bus·Error detection - and·On-chip line receiver·Input hysteresis of at least 2 volts·Test lnputs bypass analog inputs·Simplified lightning protection with the ability to ...
HI-8685: Features: ·Automatic conversion of serial ARINC 429, 575 & 561 data to 16-bit parallel data·High speed parallel 16-bit data bus·Error detection - and·On-chip line receiver·Input hysteresis of at...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
DescriptionHI-8010J-85 is a 32 segment high voltage display driver constructed of MOS P Channel an...
·Automatic conversion of serial ARINC 429, 575 & 561 data to 16-bit parallel data
·High speed parallel 16-bit data bus
·Error detection - and
·On-chip line receiver
·Input hysteresis of at least 2 volts
·Test lnputs bypass analog inputs
·Simplified lightning protection with the ability to add 10 Kohm external series resistors
·Small, package options:
·SOIC, TQFP and PLCC
·Military processing available word length parity
·Reset input for power-on initialization surface mount, plasti
The HI-8685 and HI-8686 are system components for interfacing incoming ARINC 429 signals to 16-bit parallel data using proven +5V analog/digital CMOS technology. Both products incorporate the digital logic and analog line receiver circuitryinasingledevice.
The receivers on the HI-8685 and the HI-8686 connect directly to the ARINC 429 Bus and translate the incoming signals to normal CMOS levels. Internal comparator levels are set just below the standard 6.5 volt minimum data thresholdandjust abovethestandard2.5volt maximumnull threshold. The -10 version of the HI-8685 allows the incorporation of an external 10K resistance in series with each ARINC input for lightning protection without affecting ARINClevel detection.
Both HI-8685 products offer high speed 16-bit parallel bus interface, a32-bit buffer, anderror detectionfor wordlengthandparity. Areset pinis alsoprovidedfor power-oninitialization.