HI-8581 / HI-8589

The HI-8581 / HI-8589 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interegating the a receiver. The data bus interfaces with both CMOS & TTL.

In the HI-8581 / HI-8589 series, the HI-8581 has 37.5 ohms in series with each line driver output. The HI-8589 provides the option to bypass most of the internal output resistance so that external series resistance may be added for lightning protection while still matching the 75 ohm characteristic impedance of the ARINC bus.

Each independent receiver monitors the data stream with a sampling rate of 10 times the data rate. The sampling rate is software selectable at either 1 MHz (High Speed) or 125 KHz (Low Speed). The results of a parity check are available as the 32 ARINC bit. The HI-8581 and HI-8589 examine the null and data timings and will reject erroneous patterns. For example, with a 125 KHz (Low Speed) clock selection, the incoming data frequency must be between 10.4 KHz and 15.6 KHz.

The HI-8581 / HI-8589 transmitter has a First In, First Out (FIFO) memory to store 8 ARINC words for transmission. The data rate of the transmitter is software selectable by dividing the master clock, CLK, by either 10 or 80. The master clock is used to set the timing of the ARINC Transmission within the required resolution.