Features: ·ARINC specification 429 compatible·Direct receiver and transmitter interface to·ARINC bus in a single device.·16-Bit parallel data bus.·Timing control 10 times the data rate·Selectable data clocks·Receiver error rejection per ARINC·specification 429·Automatic transmitter data timing·Sel...
HI-8281: Features: ·ARINC specification 429 compatible·Direct receiver and transmitter interface to·ARINC bus in a single device.·16-Bit parallel data bus.·Timing control 10 times the data rate·Selectable da...
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DescriptionHI-8010J-85 is a 32 segment high voltage display driver constructed of MOS P Channel an...
The HI-8281 device fromHolt Integrated Circuits is a silicon gate CMOS device for interfacing a 16-bit parallel data bus directly to the ARINC 429 serial bus. The HI-8281 provides two receivers, an independent transmitter and line driver capability in a single package. The receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol. The transmitter section provides the ARINC 429 communicationprotocol andthe linedriver circuits provide theARINC429 output levels.
The HI-8281 16-bit parallel data bus exchanges the 3 2-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The data bus interfaces with CMOSandTTL. Timing of all the circuitry begins with the master clock input, CLK. For ARINC 429 applications, the master clock frequency is1MHz.
Each HI-8281 independent receiver monitors the data streamwith a sampling rate 10 times the data rate. The sampling rate is software selectable at either 1MHz or 125KHz. The results of a parity check are available as the 32nd ARINCbit. The HI-8281 examines the null and data timings and will reject erroneous patterns. For exam ple, with a 125 KHz clock selection, the data frequency must be between 10.4 KHz and15.6KHz.
The HI-8281 transmitter has a First In, First Out (FIFO) memory to store8ARINCwords for transmission. Thedatarateof the transmitter is software selectable by dividing the master clock, CLK, by either 10 or 80. The master clock is used to set thetimingof theARINCtransmissionwithintherequired resolution.