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HI-5700

Features: • 20 MSPS with No Missing Codes• 18MHz Full Power Input Bandwidth• No Missing Codes Over Temperature• Sample and Hold Not Required• Single +5V Supply Voltage• CMOS/TTL• Overflow Bit• Improved Replacement for MP7684• Evaluation Board A...

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SeekIC No. : 004362430 Detail

HI-5700: Features: • 20 MSPS with No Missing Codes• 18MHz Full Power Input Bandwidth• No Missing Codes Over Temperature• Sample and Hold Not Required• Single +5V Supply Voltage&...

HI-5700 Data Sheet

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Part Number:
HI-5700
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/10/17

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Product Details

Description



Features:

• 20 MSPS with No Missing Codes
• 18MHz Full Power Input Bandwidth
• No Missing Codes Over Temperature
• Sample and Hold Not Required
• Single +5V Supply Voltage
• CMOS/TTL
• Overflow Bit
• Improved Replacement for MP7684
• Evaluation Board Available
• /883 Version Available


Application

• Video Digitizing
• Radar Systems
• Medical Imaging
• Communication Systems
• High Speed Data Acquisition Systems


Pinout

Connection Diagram


Specifications

Supply Voltage, VDD to GND . . . . . . . . .  . . . . . . . .(GND - 0.5) < VDD < +7.0V
Analog and Reference Input Pins. . . . . . . . . (VSS - 0.5) < VINA < (VDD +0.5V)
Digital I/O Pins . . . . . . . . . . . . . . .  . . . . . . .(GND - 0.5) < VI/O < (VDD +0.5V)
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .  -65 to +150
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . .  . . . . . . . 300



Description

The HI-5700 is a monolithic, 8-bit, CMOS Flash Analog-to- Digital Converter. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 20 MSPS speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit.

The HI-5700 delivers ±0.5 LSB differential nonlinearity while consuming only 725mW typical) at 20 MSPS. Microprocessor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. An overflow bit is provided to allow the series connection of two converters to achieve 9-bit resolution.




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