HEF4526B

The HEF4526B is a synchronous programmable 4-bit binary down counter with an active HIGH and an active LOW clock input (CP₀, CP₁), an asynchronous parallel load input (PL), four parallel inputs (P₀ to P₃), a cascade feedback input (CF), four buffered parallel outputs (O₀ to O₃), a terminal count output (TC) and an overriding asynchronous master reset input (MR).

This HEF4526B is a programmable, cascadable down counter with a decoded TC output for divide-by-n applications. In single stage applications the TC output is connected to PL. CF allows cascade divide-by-n operation with no additional gates required.

Information on P₀ to P₃ is loaded into the counter while PL is HIGH, independent of all other input conditions except MR, which must be LOW. When PL and CP₁ are LOW, the counter advances on a LOW to HIGH transition of CP₀.When PL is LOW and CP₀ is HIGH, the counter advances on a HIGH to LOW transition of CP₁. TC is HIGH when the counter is in the zero state (O₀ = O₁ = O₂ = O₃ = LOW) and CF is HIGH and PL is LOW. A HIGH on MR resets the counter (O₀ to O₃ = LOW) independent of other input conditions.  Schmitt-trigger action in the clock input makes the HEF4526B circuit highly tolerant to slower clock rise and fall times.