HD74LS190

The HD74LS190 is designed as synchronous up/down decade counters (single clock line). Synchronous operation of HD74LS190 is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.

Some recommended operating conditions of HD74LS190 have been concluded into several points as follow. The first one is about its clock frequency which would be min 0 and max 20MHz. The second one is about its clock pulse width which would be min 25ns. The third one is about its load input pulse width which would be min 35ns. The fourth one is about its setup time which would be min 20ns. The fifth one is about its hold time which would be min 3ns. The sixth one is about its enable time which would be min 40ns.

And some electrical characteristics about HD74LS190. The first one is about its input voltage which would be min 2.0V for high level and would be max 0.8V for low level. The second one is about its output voltage which would be min 2.7V for high level and max 0.4V for Iol=4mA low level and would be max 0.5V for Iol=8mA low level. The third one is abut its input current which would be max 60uA for enable and max 20uA for others with condition of Vcc=5.25V and Vi=2.7V and would be max -1.2mA for enable and max -0.4mA for others with condition of Vcc=5.25V and Vi=0.4V. The fourth one is about its short circuit output current which would be min -20mA and max -100mA. The fifth one is about its supply current which would be typ 20mA and max 35mA. The sixth one is about its input clamp voltage which would be max -1.5V. And so on. For more information please contact us.