HD74LS162A

    This synchronous decade counter features an internal carry look-ahead to appliation in high-speed counting designs. Synchronous operation is provided by having all flip-flops clock simultaneous so that the outputs change coincident with each other when so instructed by the countable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with  asychronous (ripple clock ) counters. A buffered clock input triggers the four flip-flops on the rising (positive -going) edge of the clock input waveform. This HD74LS162A counter is fully programmable ; that is , the outputs may be preset to either level . As presetting is synchronous , setting up a low level at the load input disables the counter and causes the outputs to agree with  the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transistors at the load input would be avoided when the clock is low if the enable inputs are high at or before the transition .  The clear function is asychronous and a low level at the clear inputs sets all four of the flip-flop outputs low after the next clock pulse, regradless of the levels of the enable inputs. This sychronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to LLLL. Low-to-high transistors at the clear input should be avoided when the clock is low if the ebale and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synshronous applications without additional ating. Instrumenttal in accomplishing this function are two countable inputs and a ripple carry output. Both count-enbale inputs (P and T) must be high to count , and input T is fed forward to enable the ripple carry output. The ripple carry outputs thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output .There are some recommended operating conditions about it . Clock frequency is 0 min and 25 MHz max. Clock pulse width is 25 ns min . Hold time is 3 ns min . Besides, there are also some electricla characteristics about it when Ta is -20 to +75. Input voltage is 2.0 V min. Short-circuit output current is 20 mA min and 100 mA max when Vcc is 5.25 V. Supply current is 18 mA typ and 31 mA max when Vcc is 5.25 V. Input clamp voltage is 1.5 V max when Vcc is 4.75 V and ILS is -18 mA .
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