HD74HCT533

`  LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
`  High Speed Operation: t_pd (Data to Q) = 14 ns typ (C_L = 50 pF)
`  High Output Current: Fanout of 15 LSTTL Loads
`  Wide Operating Voltage: V_CC = 4.5 to 5.5 V
`  Low Input Current: 1 A max
`  Low Quiescent Supply Current: I_CC (static) = 4 A max (Ta = 25°C)

When the HD74HCT533 latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals present at the other inputs and the state of the storage elements.