HD74ALVCH16825

Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

The HD74ALVCH16825 improves the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The HD74ALVCH16825 can be used as two 9-bit buffers or one 18-bit buffer. It provides true data. The 3-state control gate is a 2-input AND gate with active low inputs so that if either output enable (OE1 or OE2) input is high, all nine affected outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.