HD74ALVCH16721

Features:

·  VCC = 2.3 V to 3.6 V
·  Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
·  Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
·  High output current ±24 mA (@VCC = 3.0 V)
·  Bus hold on data inputs eliminates the need for external pullup / pulldown resistors


Pinout




Specifications

Item	Symbol	Ratings	Unit	Conditions
Supply voltage range	VCC	-0.5 to 4.6	V
Input voltage range *1	VI	-0.5 to 4.6	V
Output voltage range *1, 2	VO	-0.5 to VCC+0.5	V	Output : H or L
		-0.5 to 4.6	V	VCC : OFF
Input clamp current	IIK	-50	mA	VI < 0
Output clamp current	IOK	±50	mA	VO < 0 or VO > VCC
Continuous output current	IO	±50	mA	VO = 0 to VCC
Continuous current through VCC or GND	ICC or IGND	±100	mA
Maximum power dissipation at Ta = 25°C (in still air) *3	PT	200	mW
Storage temperature	Tstg	-65 to 150	°C

Description

The HD74ALVCH16721's twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the HD74ALVCH16721 provides true data at the Q outputs, provided that the clock enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output enable (OE) input can be used to place the twenty outputs in either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) input does not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.