HD74ALVCH16543

Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

The HD74ALVCH16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch enable (LEAB or LEBA) and output enable (OEAB or OEBA) inputs are provided for each HD74ALVCH16543 register to permit independent control in either direction of data flow. The A to B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A to B latches are transparent; a subsequent low to high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using CEBA, LEBA, and OEBA. Active HD74ALVCH16543 bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.