HD74ALVCH162827

Features:

*  V_CC = 2.3 V to 3.6 V
*  Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25 C)
*  Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25 C)
*  High output current 12 mA (@V_CC = 3.0 V)
*  Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
*  All outputs have equivalent 26 W  series resistors, so no external resistors are required.


Pinout




Specifications

Item	Symbol	Ratings	Unit	Conditions
Supply voltage	VCC	0.5 to 4.6	V
Input voltage*1	VI	0.5 to 4.6	V
Output voltage *1, 2	VO	0.5 to VCC +0.5	V
Input clamp current	IIK	50	mA	VI < 0
Output clamp current	IOK	50	mA	VO < 0 or VO > VCC
Continuous output current	IO	50	mA	VO = 0 to VCC
VCC , GND current / pin	ICC or IGND	100	mA
Maximum power dissipation at Ta = 55 C (in still air)*3	PT	1	W	TSSOP
Storage temperature	Tstg	65 to 150	C

Description

The HD74ALVCH162827 is composed of two 10-bit sections with separate output enable signals.  For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active.  If either output enable input is high, the outputs of that 10-bit buffer section are in the high impedance state.  Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  All outputs of HD74ALVCH162827 are designed to sink up to 12 mA, include 26 W  resistors to reduce overshoot and undershoot.