HD74ALVCH16269

Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.

The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port. The HD74ALVCH16269 is particularly suitable as an interface between synchronous DRAMs and high speed microprocessors. Data is stored in the internal B port registers on the low to high transition of the clock (CLK) input when the appropriate clock enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B to A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The HD74ALVCH16269 register on the A output permits the fastest possible data transfer, thus extending the period that the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active low output enables (OEA, OEB1, OEB2). Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.