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HD74ALVCH16245

Features: * VCC = 2.3 V to 3.6 V* Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 C)* Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25 C)* Bus hold on data inputs eliminates the need for external pullup / pulldown resistorsPinoutSpecifications Item Symbol Ratings Unit ...

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HD74ALVCH16245: Features: * VCC = 2.3 V to 3.6 V* Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 C)* Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25 C)* Bus hold on data inputs eliminates the ...

HD74ALVCH16245 Data Sheet

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Part Number:
HD74ALVCH16245
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

*  VCC = 2.3 V to 3.6 V
*  Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 C)
*  Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25 C)
*  Bus hold on data inputs eliminates the need for external pullup / pulldown resistors


Pinout

Connection Diagram


Specifications

Item Symbol Ratings Unit Conditions
Supply voltage VCC 0.5 to 4.6 V  

Input voltage *1, 2		 VI 0.5 to 4.6 V Except I/O ports
0.5 to VCC +0.5 I/O ports

Output voltage *1, 2		 VO 0.5 to VCC +0.5
 V  
Input clamp current IIK 50
 mA VI < 0
Output clamp current IOK 50 mA VO < 0 or VO > VCC
Continuous output current IO 50
 mA VO = 0 to VCC
VCC , GND current / pin
 ICC or IGND
 		 100
 mA  
Maximum power dissipation

at Ta = 55 C (in still air)*3 		PT 0.85
 W TSSOP
Storage temperature Tstg 65 to 150 C  



Description

The HD74ALVCH16245 is designed for asynchronous communication between data buses.  The control function implementation minimizes external timing requirements.  This HD74ALVCH16245 can be used as two 8-bit transceivers or one 16-bit transceiver.  It allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input.  The output enable (OE) input can be used to disable the device so that the buses are effectively isolated.  Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.




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