Features: ` Supports PC133 and meets PC SDRAM registered DIMM specification, Rev. 0.9 ` VCC = 2.3 V to 3.6 V` Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)` Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)` High output current ±12 mA (@VCC = 3.0 V)` All outputs have se...
HD74ALVCF162834: Features: ` Supports PC133 and meets PC SDRAM registered DIMM specification, Rev. 0.9 ` VCC = 2.3 V to 3.6 V` Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)` Typical VOH undershoot ...
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Item | Symbol | Ratings | Unit | Conditions |
Supply voltage range | vcc | 0.5 to 4.6 | V | |
Input voltage range *1 |
vi | 0.5 to 4.6 | V | |
Output voltage range * | vo | 0.5 to VCC+0.5 | V | |
Input clamp current | lik | -50 | mA | VI < 0 |
Output clamp current | LOK | ±50 | mA | VO < 0 or VO > VCC |
Continuous output current | LO | ±50 | mA | VO = 0 to VCC |
VCC, GND current / pin | LCC LGND | ±100 | mA | |
Maximum power dissipation at Ta = 55°C (in still air) *3 |
PT | 1 | W | TSSOP |
Storage temperature range | TSTG | 65 to 150 | °C |
The HD74ALVCF162834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation.
Data flow from A to Y is controlled by the output enable (OE). The HD74ALVCF162834 operates in the transparent mode when the latch enable (LE) is low. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is high, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup registor; the minimum value of the HD74ALVCF162834 registor is determined by the current sinking capability of the driver.All outputs, which are designed to sink up to 12 mA, include series resistors to reduce overshoot and undershoot.