HD74ALVC162835

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating condition" is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. The input and output positive-voltage ratings may be exceeded up to 4.6 V if the input and output clamp-current ratings are observed.
3. The maximum power dissipation is calculated using a junction temperature of 150°C and board trace length of 750 mils.

The HD74ALVC162835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V_CC operation.

Data flow from A to Y is controlled by the output enable (OE). The HD74ALVC162835 operates in the transparent mode when the latch enable (LE) is high. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is low, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state.

To ensure the high impedance state during power up or power down, OE should be tied to V_CC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the driver.

All outputs of HD74ALVC162835 which are designed to sink up to 12 mA, include 26 resistors to reduce overshoot and undershoot.