HD-4702

Features:

• HD-4702 Provides 13 Commonly Used Bit Rates
• Uses a 2.4576MHz Crystal/Input for Standard Frequency Output (16 Times Bit Rate)
• Low Power Dissipation
• Conforms to EIA RS-404
• One HD-4702 Controls up to Eight Transmission Channels
• Initialization Circuit Facilitates Diagnostic Fault Isolation
• On-Chip Input Pull-Up Circuit




Pinout






Specifications

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . +8.0V
Input, Output or I/O Voltage . . . . .GND -0.5V to V_CC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Typical Derating Factor . . . . . . 1mA/MHz Increase in ICCOP




Description

The HD-4702 Bit Rate Generator provides the necessary clocksignals for digital data transmission systems, such as a UART. Itgenerates 13 commonly used bit rates using an on-chip crystaloscillator or an external input. For conventional operation generating16 output clock pulses per bit period, the input clock frequencymust be 2.4576MHz (i.e. 9600 Baud x 16 x 16, sincethere is an internal 16 prescaler). A lower input frequency willresult in a proportionally lower output frequency.The HD-4702 can provide multi-channel operation with a minimumof external logic by having the clock frequency CO and the 8 prescaler outputs Q0, Q1, Q2 available externally. All signalshave a 50% duty cycle except 1800 Baud, which has less than0.39% distortion.The four rate select inputs (S0-S3) select which bit rate is at theoutput (Z). See Truth Table for Rate Select Inputs for select codeand output bit rate. Two of the 16 select codes for the HD-4702 donot select an internally generated frequency, but select an inputinto which the user can feed either a different frequency, or astatic level (High or Low) to generate ZERO BAUD.The bit rates most commonly used in modern data terminals(110, 150, 300, 1200, 2400 Baud) require that no more than oneinput be grounded for the HD-4702, which is easily achieved witha single 5-position switch.The HD-4702 has an initialization circuit which generates a masterreset for the scan counter. This signal is derived from a digitaldifferentiator that senses the first high level on the CP input afterthe ECP input goes low. When ECP is high, selecting the crystalinput, CP must be low. A high level on CP would apply a continuousreset. See Clock Modes and Initialization below.