HCTS161AMS

Features:

• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• Minimum LET for SEU Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/B
Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
-VIL = 0.8V Max
-VIH = VCC/2V Min
• Input Current Levels Ii 5µA at VOL, VOH


Pinout




Specifications

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7.0V
Input Voltage Range, All Inputs  . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input  . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1


Description

The Intersil HCTS161AMS high-reliability high-speed presettable four-bit binary synchronous counter features asynchronous reset and look-ahead carry logic. The HCTS161AMS has an active-low master reset to zero, MR. A low level at the synchronous parallel enable, SPE, disables counting and allows data at the preset inputs (P0 - P3) to load the counter. The data is latched to the outputs on the positive edge of the clock input, CP. The HCTS161AMS has two count enable pins, PE and TE. TE also controls the terminal count output, TC. The terminal count output
indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count.
The HCTS161AMS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS161AMS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).