HCTS160T

Features: • QML Class T, Per MIL-PRF-38535• Radiation Performance- Gamma Dose () 1 x 105 RAD(Si)- Latch-Up Free Under Any Conditions- SEP Effective LET No Upsets: >100 MEV-cm2/mg- Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)• 3 Micron Radiation Hardened...

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SeekIC No. : 004359935 Detail

HCTS160T: Features: • QML Class T, Per MIL-PRF-38535• Radiation Performance- Gamma Dose () 1 x 105 RAD(Si)- Latch-Up Free Under Any Conditions- SEP Effective LET No Upsets: >100 MEV-cm2/mg- Sin...

floor Price/Ceiling Price

Part Number:
HCTS160T
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• QML Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose () 1 x 105 RAD(Si)
- Latch-Up Free Under Any Conditions
- SEP Effective LET No Upsets: >100 MEV-cm2/mg
- Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
• 3 Micron Radiation Hardened SOS CMOS
• Fanout (Over Temperature Range)
- Standard Outputs 10 LSTTL Loads
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii  5mA at VOL, VOH



Pinout

  Connection Diagram


Description

Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These HCTS160T QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability.

The Intersil HCTS160T is a Radiation Hardened High Speed Presettable BCD Decade Synchronous Counter that features an asynchronous reset and look-ahead carry logic. Counting and parallel presetting are accomplished synchronously with the low-to-high transition of the clock. A low level on the synchronous parallel enable input, SPE, disables counting and allows data at the preset inputs, P0 - P3, to be loaded into the counter. The HCTS160T counter is reset by a low on the master reset input, MR. Two count enables, PE and TE are provided for n-bit cascading. TE also controls the terminal count output, TC. The terminal count output indicates a maximum count for one clock pulse and is used to enable the next cascaded stage to count.




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