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HCTS138DMSR

Features: • 3 Micron Radiation Hardened SOS CMOS• Total Dose 200K RAD (Si)• SEP Effective LET No Upsets: >100 MEV-cm2/mg• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit- Day (Typ)• Latch-Up Free Under Any Conditions• Fanout (Over Temperature Range...

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SeekIC No. : 004359926 Detail

HCTS138DMSR: Features: • 3 Micron Radiation Hardened SOS CMOS• Total Dose 200K RAD (Si)• SEP Effective LET No Upsets: >100 MEV-cm2/mg• Single Event Upset (SEU) Immunity < 2 x 10-9 E...

HCTS138DMSR Data Sheet

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Part Number:
HCTS138DMSR
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit- Day (Typ)
• Latch-Up Free Under Any Conditions
• Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
• Military Temperature Range: -55 to +125
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii 5µA at VOL, VOH


Pinout

Connection Diagram


Specifications

Supply Voltage (VCC) . . . . . . . . . . . . . . . . .  . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . -0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . .. . . . . . . ±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . ±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . -65 to +150
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . .  . .+265
Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . .. . . .+175
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1


Description

The Intersil HCTS138MS is a Radiation Hardened 3-to-8 line Decoder/Demultiplexer. The outputs are active in the low state. Two active low and one active high enables (E1, E2, E3) are provided. If the device is enabled, the binary inputs (A0, A1, A2) determine which one of the eight normally high outputs will go to a low logic level.

The HCTS138MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCTS138MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).




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