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HCTS109DMSR_1192662

Features: • 3 Micron Radiation Hardened SOS CMOS• Total Dose 200K RAD (Si)• SEP Effective LET No Upsets: >100 MEV-cm2/mg• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)• Dose Rate Survivability: >1 x 1012 RAD (Si)/s• Dose Rate Upset &...

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HCTS109DMSR_1192662: Features: • 3 Micron Radiation Hardened SOS CMOS• Total Dose 200K RAD (Si)• SEP Effective LET No Upsets: >100 MEV-cm2/mg• Single Event Upset (SEU) Immunity < 2 x 10-9 E...

HCTS109DMSR_1192662 Data Sheet

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Part Number:
HCTS109DMSR_1192662
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Logic Compatibility
-VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii 5µA at VOL, VOH


Pinout

Connection Diagram Connection Diagram




Specifications

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . .  . -0.5V to +7.0V
Input Voltage Range, All Inputs  . . . . . . . . . . . -0.5V to VCC +0.5V
DC Input Current, Any One Input  . . . . . . . . . . . . . . . . . . ..±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . ..±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . .  -65 to +150
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . .      +
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1


Description

The Intersil HCTS109MS is a Radiation Hardened Dual JK lip Flop with set and reset. The flip flop changes state with he positive transition of the clock (CP1 or CP2).

The HCTS109MS utilizes advanced CMOS/SOS technology o achieve high-speed operation. This device is a member of adiation hardened, high-speed, CMOS/SOS Logic Family. he HCTS109MS is supplied in a 16 lead Ceramic flatpack K suffix) or a SBDIP Package (D suffix).




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