HCT259

Features:

• Optimized for low voltage applications: 1.0 to 3.6 V
• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,Tamb = 25°C
• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,Tamb = 25°C
• Combines demultiplexer and 8-bit latch
• Serial-to-parallel capability
• Output from each storage bit available
• Random (addressable) data entry
• Easily expandable
• Common reset input
• Useful as a 3-to-8 active HIGH decoder
• Output capability: standard
• ICC category: MSI


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	RATING	UNIT
VCC	DCsupply voltage		0.5 to +4.6	V
±IIK	DC input diode current	VI <0.5 or VI > VCC + 0.5V	20	mA
±IOK	DC output diode current	VO < 0.5 or VO >VCC + 0.5V	50	mA
±IO	DC output source or sink current standard outputs	0.5V < VO < VCC + 0.5V	25	mA
±IGND, ±ICC	DC VCC or GND current for types with standard outputs		50	mA
Tstg	Storage temperature range		65 to +150
PTOT	Power dissipation per package plastic DIL plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP)	for temperature range: 40 to +125 above +70 derate linearly with 12 mW/K above +70 derate linearly with 8 mW/K above +60 derate linearly with 5.5 mW/K	750 500 400	mW

NOTES:
           1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
           2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.


Description

The 74LV259 is a low-voltage CMOS device and is pin and function compatible with 74HC/HCT259.The 74LV259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. The 74LV259 is a multifunction device capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and
demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available. The 74LV259 also incorporate an active LOW common reset (MR) for resetting all latches, as well as an active LOW enable input (LE). The 74LV259 has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the
address (A0 to A2) and date (D) input. When operating the 74LV259 as an addressable latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the 74LV259.