HCS190HMSR

The Intersil HCS190MS is an asynchronously presettable BCD Decade synchronous counter. Presetting the counter to the number on the preset data inputs (P0 - P3) is accomplished by a low on the parallel load input (PL). Counting occurs when (PL) is high, Count Enable (CE) is low and the Up/Down (U/D) input is either low for up-counting or high for down-counting. The HCS190MS counter is incremented or decremented synchronously with the low-to-high transition of the clock. When an overflow or underflow of the counter occurs, the Terminal Count output (TC), which is low during counting, goes high and remains high for one clock cycle. This output can be used for lookahead carry in high speed cascading. The TC output also initiates the Ripple Clock output (RC) which, normally high, goes low and remains low for the low-level portion of the clock pulse. These counter can be cascaded using the Ripple Carry output. If the decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one or two counts. The HCS190MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS190MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).