HCS12H

• HCS12 Core
HCS12 16-bit CPU
• Upward compatible with M68HC11 instruction set
• Interrupt stacking and programmer's model identical to M68HC11
• Instruction queue
• Enhanced indexed addressing
HCS12 MEBI (Multiplexed Expanded Bus Interface)
HCS12 MMC (Module Mapping Control)
HCS12 INT (Interrupt Control)
HCS12 BKP (On-chip Breakpoints)
HCS12 BDM (Single-wire Background Debug™ Mode)
• Memory options
32K, 64K, 128K, 256K byte Flash EEPROM or 64K, 128K, 192K and 256K byte ROM
2K, 4K, 6K, 8K, 12K byte RAM
2K, 4K byte EEPROM on Flash versions only
• 8-bit and 4-bit ports with Interrupt capability
Digital filtering
Programmable rising or falling edge trigger
• Clock Reset Generator (CRG)
Low current Colpitts or Pierce oscillator (0.5 to 16Mhz reference clock)
Phase-locked loop clock frequency multiplier
Windowed COP watchdog and Clock Monitor resets
Real Time Interrupt
• Up to 16-channels Analog-to-Digital Converter (ADC)
10-bit resolution
External conversion trigger capability
• Up to two 1M bit per second, CAN 2.0 A, B software compatible modules (MSCAN12)
Five receive and three transmit buffers
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
Four separate interrupt channels for Rx, Tx, error and wake-up
Low-pass filter wake-up function
Loop-back for self test operation
• Timer (TIM)
16-bit main counter with 7-bit prescaler
Eight programmable input capture or output compare channels
Two 8-bit or one 16-bit pulse accumulators
• Up to six Pulse Width Modulator (PWM) channels
Programmable period and duty cycle for each channel
Pairs of 8-bit channels can be concatenated as one 16-bit channel
Center-aligned or left-aligned outputs
Wide range of programmable clock frequencies
Fast emergency shutdown input
• Serial interfaces
Up to two asynchronous Serial Communications Interfaces (SCI)
Synchronous Serial Peripheral Interface (SPI)
Inter-IC Bus Interface (IIC)
• Liquid Crystal Display (LCD) driver
Up to 32 frontplanes and 4 backplanes
5 modes of operation allow for different display sizes to meet application requirements
Programmable frame clock generator and bias voltage level
• 16 or 24 high current drivers suited for PWM motor control
Each PWM channel switchable between two drivers in an H-bridge configuration
Support for sine and cosine drive
11-bit resolution with selectable dithering function
Left, right or center aligned outputs
Slew rate control
• Up to four Stepper Stall Detectors (SSD) - available on selected devices
Flexible full step and polarity set up to return the pointer to its reset position in clockwise or counter clockwise direction.
Integrator/Sigma Delta converter circuit to measure the induced voltage by the back EMF of unpowered coil during full step (only one of the two motor coils is powered) operation.
16-Bit Down Counter to monitor blanking and integration time to support stepper motors with different gear ratios.
16-Bit accumulator register to read integration value, compare to a threshold at the end of integration time, and decide if the motor is stalled under this value or moving above this value.
• Operating Frequency
32Mhz equivalent to 16Mhz Bus Speed (Only 9S12H256)
50Mhz equivalent to 25Mhz Bus Speed (Except 9S12H256)
• 80-Pin, 112-Pin or 144-Pin QFP package
I/O lines with 5V input and drive capability
5V A/D converter inputs
• Flash emulation of ROM versions
ROM versions 3S12HZ256, 3S12HZ192, 3S12HZ128 and 3S12HN128 should use the 9S12HZ256 for Flash emulation.
ROM versions 3S12HZ64, 3S12HN64, 3S12HZ32 and 3S12HN32 should use the 9S12HZ64 for Flash emulation.
• Pin out explanations:
A/D is the number of A/D channels.
PWM is the number of TIM channels.
LCD denotes the number of front planes times the number of back planes.
Motor denotes the number of high current drive pins / number of stepper motors which can be driven
SSD denotes whether this device features a Stepper Stall Detection Circuit
Versions with one SCI will use SCI0
Versions with one CAN will use CAN0
I/O is the sum of ports capable to act as digital input or output.
144 Pin Package:
Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 5, L = 8, M = 6, P = 6, S = 8, T = 8, U = 8, V = 8, W = 8, PAD = 16 input only.
14 inputs provide Interrupt capability (H = 8, J = 4, IRQ, XIRQ).
112 Pin Package for H Versions:
Port A = 8, B = 8, E = 6 + 2 input only, K = 5, L = 4, M = 4, P = 2, S = 6, T = 8, U = 8, V = 8, W = 8, PAD = 8 input only.
2 inputs provide Interrupt capability (IRQ, XIRQ).
112 Pin Package for 9HZ256, 9HZ128, 3HZ128 and 3HN128 Versions:
Port A = 8, B = 8, E = 6 + 2 input only, K = 5, L = 8, M = 5, P = 6, S = 6, T = 8, U = 8, V = 8, PAD = 8.
10 inputs provide Interrupt capability (AD = 8, IRQ, XIRQ).
112 Pin Package for 9HZ64, 9HN64, 3HZ64 and 3HN64 Versions:
Port A = 8, B = 4, E = 4 + 1 input only, K = 5, L = 4, M = 2, P = 4, S = 5, T = 8, U = 8, V = 8, PAD = 8. 9 inputs provide Interrupt capability (AD = 8, XIRQ).
80 Pin Package for 9HZ64, 9HN64, 3HZ32 and 3HN32 Versions:
Port A = 8, B = 4, E = 4 + 1 input only, K = 5, M = 2, P = 4, S = 5, T = 4, U = 8, V = 8, PAD = 7. 8 inputs provide Interrupt capability (AD = 7, XIRQ).
• Compatibility Considerations
Pins associated with Motors 0 and 5 should be left unconnected to ensure compatibility with versions featuring 4 Motors.

Designed for automotive instrumentation applications, all members of the MCS12H-Family of microcontroller units (MCU) are composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 256K bytes of Flash EEPROM or ROM, up to 12K bytes of RAM, up to 4K bytes of EEPROM on Flash parts, one or two asynchronous serial communications interfaces (SCI), a serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit analog-to-digital converter (ADC), up to six-channel pulse width modulator (PWM), and up to two CAN 2.0 A, B software compatible modules. In addition, they feature a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width modulator (MC) consisting of up to 24 high current outputs suited to drive up to six stepper motors, and on selected devices, up to four stepper stall detectors (SSD) to simulataneously calibrate the pointer reset position of each motor. The MCS12H-Family has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each MCS12H-Family  module, up to 14 I/O ports are available with Key-Wake-Up capability from STOP or WAIT mode.