HCS112D

Features:

• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/ Bit-Day (Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current Levels Ii 5µA at VOL, VOH


Pinout




Specifications

Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . .  . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . .. . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . .. . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150
Lead Temperature (Soldering 10sec) . . . . . . . . . . . .. . . . . . +265
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1


Description

The Intersil HCS112MS is a Radiation Hardened dual JK flip-flop with set and reset. The output changes state on the negative going transition of the clock pulse. Set and reset are accomplished asynchronously by a logic low input level.

The HCS112MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCS112MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix).