Features: - VTTL compatible inputs and outputs- 10 bit Column addressing- Single 3.3V +/- .3 power supply- Buffered Address and Control lines- Mezzanine stackingAccess time: 60 ns (max)- Power dissipation* Active: 7.5 W (max)* Standby : 400 mW (max) (CMOS interface)- EDO page mode capability- CAS-...
HCPMEM-512: Features: - VTTL compatible inputs and outputs- 10 bit Column addressing- Single 3.3V +/- .3 power supply- Buffered Address and Control lines- Mezzanine stackingAccess time: 60 ns (max)- Power dissi...
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The HCPMEM-512 is a 32M x 144 bit Dynamic RAM high-density module, organized with four banks of 8M x 144 bits.
The HCPMEM-512 consists of thirty six 8M x 16, 4K refresh DRAMs in TSOPII packages, five 16 bit buffer/drivers and one PLD. The PLD controls the WRITE Enable and Output Enable signals to the DRAMS. Connectors on each side of the module allow two memories to mated together.