Application·RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE-EDGE TRIGGERING.PinoutSpecifications Symbol Parameter Value Unit VDD* Supply Voltage :HCC TypesHCF Types 0.5 to + 20 0.5 to + 18 VV Vi Input Voltage 0.5 to VDD + 0.5 V II DC Input Current (a...
HCC/HCF4520B: Application·RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE-EDGE TRIGGERING.PinoutSpecifications Symbol Parameter Value Unit VDD* Supply Voltage :HCC TypesHCF Types 0.5 to ...
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PinoutSpecifications Symbol Rating Value Unit VDD* Supply Voltage : HCC Type...
PinoutSpecifications Symbol Rating Value Unit VDD* Supply Voltage : HCC Type...
PinoutSpecifications Symbol Rating Value Unit VDD* Supply Voltage : HCC Type...
Symbol |
Parameter |
Value |
Unit |
VDD* |
Supply Voltage :HCC Types HCF Types |
0.5 to + 20 0.5 to + 18 |
V V |
Vi |
Input Voltage |
0.5 to VDD + 0.5 |
V |
II |
DC Input Current (any one input) |
± 10 |
mA |
Pt ot |
Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range |
200 100 |
mW mW |
Pt ot |
Operating Temperature : HCC Types HCF Types |
55 to + 125 40 to + 85 |
°C °C |
Ts tg |
Storage Temperature |
65 to + 150 |
°C °C |
The HCC/HCF4520B (extended temperature range) and HCF4518B/4520B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4518B Dual BCD Up Counter and HCC/HCF4520B Dual BinaryUp Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable Clock and Enable lines for incrementing on either the positive-going or negative- going transition. For single-unit operation the Enable input is maintained "high" and the counter advances on each positive-going transition of the Clock. The counters are cleared by high levels on their Reset lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the clock input of the latter is held low.