HCC/HCF4042B

Features:

`CLOCK POLARITY CONTROL
`Q ANDQ OUTPUTS
`COMMON CLOCK
`LOWPOWER TTL COMPATIBLE
`STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
`QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE
`5V, 10V, AND 15V PARAMETRIC RATINGS
`INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE
`100% TESTEDFOR QUIESCENT CURRENT
`MEETSALLREQUIREMENTSOFJEDECTENTATIVESTANDARDN° 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIESCMOS DEVICES"


Pinout




Specifications

Symbol	Rating	Value	Unit
VDD*	Supply Voltage : HCC Types HCF Types	0.5 to + 20 0.5 to + 18	V V
Vi	Input Voltage	0.5 to VDD + 0.5	V
II	DC Input Current (any one input)	± 10	mA
Ptot	Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package-temperature Range	200 100	mW mW
Top	Operating Temperature : HCC Types HCF Types	55 to + 125 40 to + 85	°C °C
Tstg	Storage Temperature	65 to + 150	°C

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to V_SS pin voltage.


Description

In the HCC/HCF4042B series, the HCC4042B (extended temperature range) and HCF4042B (intermediate temperature range) are monolithic integrated circuit, available in 16-lead dual in-line plastic or ceramic package and plastic micro package.

The HCC/HCF4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.

Information present at the data of HCC/HCF4042B  input is transferred to outputs Q and Q during the CLOCK level which is programmed by the POLARITY input. For POLARITY= 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY= 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the outputs until an opposite CLOCK transition occurs.