Features: RADIATION• Fabricated with RICMOS™ IV Bulk 0.8 m Process (Leff = 0.65 m)• Total Dose Hardness through 1x106 rad(SiO2)• Neutron Hardness through 1x1014 cm-2• Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s• Soft Error Rate of <1x1...
HC6856: Features: RADIATION• Fabricated with RICMOS™ IV Bulk 0.8 m Process (Leff = 0.65 m)• Total Dose Hardness through 1x106 rad(SiO2)• Neutron Hardness through 1x1014 cm-2• D...
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Symbol |
Parameter |
Min |
Max |
Unit | |
VDD |
Positive Supply Voltage |
-0.5 |
7.0 |
V | |
VPIN |
Voltage on Any Pin |
-0.5 |
VDD+0.5 |
V | |
TSTORE |
Storage Temperature (Zero Bias) |
-65 |
150 |
||
TSOLDER |
Soldering Temperature`Time |
270`5 |
|||
PD |
Total Package Power Dissipation |
2.5 |
W | ||
IOUT |
DC or Average Output Current |
25 |
mA | ||
VPROT |
ESD Input Protection Voltage |
2000 |
V | ||
JC |
Thermal Resistance (Jct-to-Case) | 28 FP/36 FP |
2 |
/W | |
28 DIP |
10 |
/W | |||
TJ |
Junction Temperature |
175 |
The HC6856 32K x 8 Radiation Hardened Static RAM is a high performance 32,768 x 8-bit static random access memory with industry-standard functionality. HC6856 is fabricated with Honeywell's radiation hardened technology, and is designed for use in systems operating in radiation environments. The RAM operates over the full military temperature range and requires only a single 5 V ± 10% power supply. The HC6856 RAM is available with either TTL or CMOS compatible I/O. Power consumption is typically less than 50 mW/MHz in operation, and less than 5 mW/MHz in the low power disabled mode. The RAM read operation is fully asynchronous, with an associated typical access time of 20 ns.
Honeywell's enhanced RICMOS™IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of
advanced and proprietary design, layout, and process hardening techniques. The RICMOS™ IV process is a 5-volt, twin-well CMOS technology with a 170 Å gate oxide and a minimum drawn feature size of 0.8 m (0.65 m effective gate length-Leff). Additional features of HC6856 include a three layer interconnect metalization and a lightly doped drain (LDD) structure for improved short channel reliability. High resistivity cross-coupled polysilicon resistors have been incorporated for single event upset hardening.