Features: • Upward-compatibility with H8/300 and H8/300H CPUs - Can execute H8/300 CPU and H8/300H CPU object programs• General-register architecture - Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers• Sixty-five basic instructions...
H8S_2166_1219915: Features: • Upward-compatibility with H8/300 and H8/300H CPUs - Can execute H8/300 CPU and H8/300H CPU object programs• General-register architecture - Sixteen 16-bit general registers a...
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• Upward-compatibility with H8/300 and H8/300H CPUs
- Can execute H8/300 CPU and H8/300H CPU object programs
• General-register architecture
- Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
- 8/16/32-bit arithmetic and logic instructions
- Multiply and divide instructions
- Powerful bit-manipulation instructions
• Eight addressing modes
- Register direct [Rn]
- Register indirect [@ERn]
- Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
- Register indirect with post-increment or pre-decrement [@ERn+ or @ERn]
- Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
- Immediate [#xx:8, #xx:16, or #xx:32]
- Program-counter relative [@(d:8,PC) or @(d:16,PC)]
- Memory indirect [@@aa:8]
• 16 Mbytes address space
-Program: 16 Mbytes
-Data: 16 Mbytes
• High-speed operation
-All frequently-used instructions are executed in one or two states
-8/16/32-bit register-register add/subtract: 1 state
-8 * 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
-16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
-16 * 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
-32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
Rev. 3.00, 03/04, page 16 of 830
• Two CPU operating modes
- Normal mode*
- Advanced mode
Note: * Not available in this LSI.
• Power-down state
- Transition to power-down state by
- SLEEP instruction Selectable CPU clock speed
Item |
Symbol |
Value |
Unit |
Power supply voltage* |
VCC |
0.3 to +4.3 |
V |
Input voltage (except port 7, 8, C0 to C5, D6, and D7) |
Vin |
0.3 to VCC +0.3 |
|
Input voltage (port 7) |
Vin |
0.3 to AVCC +0.3 |
|
Input voltage (port 8, C0 to C5, D6, and D7) |
Vin |
0.3 to +7.0 |
|
Reference power supply voltage |
AVref |
0.3 to AVCC +0.3 |
|
Analog power supply voltage |
AVCC |
0.3 to +4.3 |
|
Analog input voltage |
VAN |
0.3 to AVCC +0.3 |
|
Operating temperature |
Topr |
Regular specifications: 20 to +75 |
|
Wide-range specifications: 40 to +85 | |||
Operating temperature (when flash memory is programmed or erased) |
Topr |
0 to +75 |
|
Storage temperature |
Tstg |
55 to +125 |
Caution: Permanent damage to this LSI may result if absolute maximum ratings are exceeded.
Note: * Voltage applied to the VCC pin.
Make sure power is not applied to the VCL pin.
The following registers are related to the operating mode. For details on the bus control register (BCR), see section 6.3.1, Bus Control Register (BCR), and for details on H8S_2166_1219915 bus control register 2 (BCR2), see section 6.3.2, Bus Control Register 2 (BCR2).
• Mode control register (MDCR)
• System control register (SYSCR)
• Serial timer control register (STCR)