H3001

• Upward compatibility with H8/300 CPU Can execute H8/300 series object programs without alteration
• General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-two basic instructions
   - 8/16/32-bit arithmetic and logic instructions
   - Multiply and divide instructions
   - Powerful bit-manipulation instructions
• Eight addressing modes
   - Register direct [Rn]
   - Register indirect [@ERn]
   - Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
   - Register indirect with post-increment or pre-decrement [@ERn+ or @ERn]
   - Absolute address [@aa:8, @aa:16, or @aa:24]
   - Immediate [#xx:8, #xx:16, or #xx:32]
   - Program-counter relative [@(d:8, PC) or @(d:16, PC)]
   - Memory indirect [@@aa:8]
• 16-Mbyte linear address space
• High-speed operation
   - All frequently-used instructions execute in two to four states
   - Maximum clock frequency: 16 MHz
   - 8/16/32-bit register-register add/subtract: 125 ns
   - 8 *8-bit register-register multiply: 875 ns
   - 16 ÷ 8-bit register-register divide: 875 ns
   - 16 * 16-bit register-register multiply: 1.375 s
   - 32 ÷ 16-bit register-register divide: 1.375 s
• Two CPU operating modes
   - Normal mode (not available in H8/3001)
   - Advanced mode
• Low-power mode Transition to power-down state by SLEEP instruction