GVT73512A8

• Fast access times: 10, 12 and 15ns
• Fast OE# access times: 5, 6and 7ns
• Single +3.3V +0.3V power supply
• Fully static -- no clock or timing strobes necessary
• All inputs and outputs are TTL-compatible
• Three state outputs
• Center power and ground pins for greater noise immunity
• JEDEC standard for functionality and revolutionary pinout
• Easy memory expansion with CE# and OE# options
• Automatic CE# power down
• High-performance, low-power consumption, CMOS double-poly, double-metal process

Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V
V_IN .........................................................-0.5V to V_CC+0.5V
Storage Temperature (plastic) ...................-55oC to +125^o
Junction Temperature ...............................................+125^o
Power Dissipation .......................................................1.2W
Short Circuit Output Current .......................................50mA

The GVT73512A8 is organized as a 524,288 x 8 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology.

GVT73512A8 offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, GVT73512A8 offers chip enable (CE#) and output enable (OE#) with this organization.

Writing to these devices is accomplished when write enable (WE#) and chip enable (CE#) inputs are both LOW. Reading is accomplished when (CE#) and (OE#) go LOW with (WE#) remaining HIGH. The GVT73512A8 offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.