GVT71256ZB36

Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V
V_IN ........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ...................-55^oC to +125^o
Junction Temperature ...............................................+125^o
Power Dissipation .......................................................2.0W
Short Circuit Output Current ......................................50mA

The GVT71256ZB36 and GVT71512ZB18 SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). GVT71256ZB36 and GVT71512ZB18 integrate 262,144x36 and 524,288x18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. The Galvantech Synchronous Burst SRAM family employs highspeed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell of GVT71256ZB36 and GVT71512ZB18 consists of four transistors and two high valued resistors.

All synchronous inputs of GVT71256ZB36 and GVT71512ZB18 are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs of GVT71256ZB36 and GVT71512ZB18 include all addresses, all data inputs, depth-expansion chip enables (CE#, CE2# and CE2), cycle start input (ADV/LD#), clock enable (CKE#), byte write enables (BWa#, BWb#, BWc# and BWd#), and read-write control (R/W#). BWc# and BWd# apply to GVT71256ZB36 only.

Address and control signals of GVT71256ZB36 and GVT71512ZB18 are applied to the SRAM during one clock cycle, and one cycle later, its associated dataoccurs, either read or write.

A clock enable (CKE#) pin allows operation of the GVT71256ZB36/GVT71512ZB18 to be suspended as long as necessary. All synchronous inputs are ignored when (CKE#) is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE#, CE2, CE2#) that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD# is low, no new memory operation of GVT71256ZB36 and GVT71512ZB18 can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus of GVT71256ZB36 and GVT71512ZB18 will be in high impedance state one cycle after chip is deselected or a write cycle is initiated.

The GVT71256ZB36 and GVT71512ZB18 have an onchip 2-bit burst counter. In the burst mode, the GVT71256ZB36 and GVT71512ZB18 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD# signal is used to load a new external address (ADV/LD#=LOW) or increment the internal burst counter (ADV/LD#=HIGH)

Output enable (OE#), snooze enable (ZZ) and burst sequence select (MODE) are the asynchronous signals. OE# can be used to disable the outputs at any given time. ZZ may be tied to LOW if GVT71256ZB36 and GVT71512ZB18 are not used.

Four pins of GVT71256ZB36 and GVT71512ZB18 are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation.