GTLP6C816A

Features:

Interface between LVTTL and GTLP logic levels
Edge Rate Control to minimize noise on the GTLP port
Power up/down high impedance for live insertion
1:6 fanout clock driver for LVTTL port
1:2 fanout clock driver for GTLP port
LVTTL compatible driver and control inputs
Flow through pinout optimizes PCB layout
Open drain on GTLP to support wired-or connection
A Port source/sink −24/+24 mA
B Port sink 50 mA
−40 to +85 temperature capability
Low voltage version of GTLP6C816


Pinout




Specifications

Supply Voltage (V_CC) ..............................−0.5V to +4.6V
DC Input Voltage (V_I) ..............................−0.5V to +4.6V
DC Output Voltage (V_O)
Outputs 3-STATE....................................  −0.5V to +4.6V
Outputs Active (Note 2)........................   −0.5V to +4.6V
DC Output Sink Current into
OA-Port I_OL........................................................ . 48 mA
DC Output Source Current
from OA-Port I_OH ...............................................−48 mA
DC Output Sink Current into
OB-Port in the LOW State I_OL ............................100 mA
DC Input Diode Current (I_IK)
V_I< 0V ................................................................−50 mA
DC Output Diode Current (I_OK)
VO < 0V ..............................................................−50 mA
VO > V_CC..........................................................  +50 mA
ESD Rating ........................................................> 2000V
Storage Temperature (T_STG) ................−65 to +150


Description

The GTLP6C816A is a clock driver that provides LVTTL toGTLP signal level translation (and vice versa). The GTLP6C816A provides a high speed interface between cards operating atLVTTL logic levels and a backplane operating at GTL(P)logic levels. High speed backplane operation is a directresult of GTL(P)'s reduced output swing (<1V), reducedinput threshold levels and output edge rate control. Theedge rate control minimizes bus settling time. GTLP is a
Fairchild Semiconductor derivative of the Gunning Trans-ceiver logic (GTL) JEDEC standard JESD8-3.Fairchild's GTL(P) has internal edge-rate control and isprocess, voltage, and temperature (PVT) compensated. Itsfunction is similar to BTL and GTL but with different outputlevels and receiver threshold. GTLP  GTLP6C816A output LOW level istypically less than 0.5V, the output level HIGH is 1.5V andthe receiver threshold is 1.0V.