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GTLP36T612

Features: Bidirectional interface between GTLP and LVTTL logiclevels Designed with edge rate control circuitry to reduce out-put noise on the GTLP port Partitioned as two 18-Bit transceivers with individuallatch timing and output control VREF pin provides external supply reference voltage forrecei...

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GTLP36T612: Features: Bidirectional interface between GTLP and LVTTL logiclevels Designed with edge rate control circuitry to reduce out-put noise on the GTLP port Partitioned as two 18-Bit transceivers with in...

GTLP36T612 Data Sheet

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Part Number:
GTLP36T612
Supply Ability:
5000

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  • 1~5000
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  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 Bidirectional interface between GTLP and LVTTL logiclevels
Designed with edge rate control circuitry to reduce out-put noise on the GTLP port
Partitioned as two 18-Bit transceivers with individuallatch timing and output control
VREF pin provides external supply reference voltage forreceiver threshold adjustibility
Special PVT compensation circuitry to provide consis-
   tent performance over variations of process, supply volt-age and temperature
TTL compatible driver and control inputs
Designed using Fairchild advanced BiCMOS technology
Bushold data inputs on A port to eliminate the need for
   external pull-up resistors for unused inputs
Power up/down and power off high impedance for liveinsertion
Open drain on GTLP to support wired-or connection
Flow through pinout optimizes PCB layout
D-type flip-flop, latch and transparent data paths
A Port source/sink −24mA/+24mA
B Port sink +50mA
For more information see AN-5026, Using BGA Packages


Specifications

Supply Voltage (VCC) ..............................−0.5V to +4.6V
DC Input Voltage (VI) ..............................−0.5V to +4.6V
DC Output Voltage (VO)
Outputs 3-STATE .....................................−0.5V to +4.6V
Outputs Active (Note 7).................. −0.5V to VCC + 0.5V
DC Output Sink Current into
A Port IOL ......................................................      .48 mA
DC Output Source Current from
A Port IOH .....................................................   ..−48 mA
DC Output Sink Current into
B Port in the LOW State, IOL ..............................100 mA
DC Input Diode Current (IIK)
VI< 0V ........................................................        −50 mA
DC Output Diode Current (IOK)
VO < 0V ........................................................      −50 mA
VO > VCC .......................................................    .+50 mA
ESD Performance................................................ >2000V
Storage Temperature (TSTG).................. −65 to +150


Description

The GTLP36T612 is an 36-bit universal bus transceiverwhich provides LVTTL to GTLP signal level translation. GTLP36T612 allows for transparent, latched and clocked modes of datatransfer. The GTLP36T612 provides a high speed interface forcards operating at LVTTL logic levels and a backplaneoperating at GTLP logic levels. High speed backplaneoperation is a direct result of GTLP's reduced output swing(< 1V), reduced input threshold levels and output edge ratecontrol. The edge rate control minimizes bus settling time.GTLP is a Fairchild Semiconductor derivative of the Gun-ning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild's GTLP GTLP36T612 has internal edge-rate control and is Pro-cess, Voltage, and Temperature (PVT) compensated. Itsfunction is similar to BTL or GTL but with different outputlevels and receiver thresholds. GTLP GTLP36T612 output LOW level isless than 0.5V, the output HIGH is 1.5V and the receiverthreshold is 1.0V.




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