GTLP18T612

The GTLP18T612 is an 18-bit universal bus transceiverwhich provides LVTTL to GTLP signal level translation. Itallows for transparent, latched and clocked modes of datatransfer. The GTLP18T612 provides a high speed interface forcards operating at LVTTL logic levels and a backplaneoperating at GTLP logic levels. High speed backplaneoperation is a direct result of GTLP's reduced output swing(< 1V), reduced input threshold levels and output edge ratecontrol. The edge rate control minimizes bus settling time.GTLP is a Fairchild Semiconductor derivative of the Gun-ning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild's GTLP GTLP18T612 has internal edge-rate control and is Pro-cess, Voltage, and Temperature (PVT) compensated. Itsfunction is similar to BTL or GTL but with different outputlevels and receiver thresholds. GTLP GTLP18T612 output LOW level isless than 0.5V, the output HIGH is 1.5V and the receiverthreshold is 1.0V.