GTLP17T616

The GTLP17T616 is a 17-bit registered bus transceiverthat provides LVTTL to GTLP signal level translation. Itallows for transparent, latched and clocked modes of datafow and provides a buffered GTLP (CLKOUT) clock outputfrom the LVTTL CLKAB. The GTLP17T616 provides a high speedinterface between cards operating at LVTTL logic levelsand a backplane operating at GTLP logic levels. Highspeed backplane operation is a direct result of GTLP'sreduced output swing (<1V), reduced input threshold levelsand output edge rate control. The edge rate control mini-mizes bus settling time. GTLP is a Fairchild Semiconductorderivative of the Gunning Transistor logic (GTL) JEDECstandard JESD8-3.

Fairchild's GTLP GTLP17T616 has internal edge-rate control and is Pro-cess, Voltage, and Temperature (PVT) compensated. Itsfunction is similar to BTL or GTL but with different outputlevels and receiver thresholds. GTLP GTLP17T616 output LOW level istypically less than 0.5V, the output level HIGH is 1.5V andthe receiver threshold is 1.0V.