Features: • FT pin for user-configurable flow through or pipelined operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 100-lead TQFP packageApplicationThe GS88018/32/36T is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Pinout
Specifications
| Symbol |
Description |
Value |
Unit |
| VDD |
Voltage on VDD Pins |
0.5 to 4. |
V |
| VDDQ |
Voltage in VDDQ Pins |
0.5 to VDD |
V |
| VCK |
Voltage on Clock Input Pin |
0.5 to 6 |
V |
| VI/O |
Voltage on I/O Pins |
0.5 to VDDQ +0.5 (£ 4.6 V max.) |
V |
| VIN |
Voltage on Other Input Pins |
0.5 to VDDQ +0.5 (£ 4.6 V max.) |
V |
| IIN |
Input Current on Any Pin |
+/20 |
mA |
| IOUT |
Output Current on Any I/O Pin |
+/20 |
mA |
| PD |
Package Power Dissipation |
1.5 |
w |
| TSTG |
Storage Temperature |
55 to 125 |
°C |
| TBIAS |
Temperature Under Bias |
55 to 125 |
°C |
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended
period of time, may affect reliability of this component.DescriptionThe GS88018/32/36T is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the GS88018/32/36T now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) of GS88018/32/36T are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles of GS88018/32/36T can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses of GS88018/32/36T can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads The function of the Data Output Register GS88018/32/36T can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge- triggered Data Output Register.
SCD Pipelined Reads The GS88018/32/36T is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs GS88018/32/36T begin turning off their outputs immediately after the deselect command has been captured in the input registers.
Byte Write and Global Write Byte write operation of GS88018/32/36T is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode Low power (Sleep mode) of GS88018/32/36T is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages The GS88018/32/36T operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit.
GS88018 Data Sheet
