GS8644Z18B-250I

Features: • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• 2.5 V or 3.3 V +10%/10% core power supply• 2.5 V or 3.3 V I/O supply̶...

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SeekIC No. : 004356128 Detail

GS8644Z18B-250I: Features: • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT...

floor Price/Ceiling Price

Part Number:
GS8644Z18B-250I
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/9/26

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Product Details

Description



Features:

• NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 9Mb, 18Mb, and 36Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165- or 209-bump BGA package



Specifications

Symbol Description Value Unit
VDD

VDDQ

VI/O

VIN

IIN

IOUT

PD

TSTG

TBIAS
Voltage on VDD Pins

Voltage in VDDQ Pins

Voltage on I/O Pins

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

Temperature Under Bias
0.5 to 4.6

0.5 to 4.6

0.5 to VDDQ +0.5 ( 4.6 V max.)

0.5 to VDD +0.5 ( 4.6 V max.)

+/20

+/20

1.5

55 to 125

55 to 125
V

V

V

V

mA

mA

W



Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.




Description

The GS8644Z18/36/72 is a 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the GS8644Z18/36/72 is switched from read to write cycles. Because GS8644Z18/36/72 is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable.

Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. GS8644Z18/36/72 feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

The GS8644Z18/36/72 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the GS8644Z18/36/72 incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.

The GS8644Z18/36/72 is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 119-bump, 165-bump or 209-bump BGA package.




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