Features: •FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package availablePinout
Specifications
| Symbol |
Description |
Value |
Unit |
| VDD |
Voltage on VDD Pins |
0.5 to 4.6 |
V |
| VDDQ |
Voltage on VDDQ Pins |
0.5 to VDD |
V |
| VI/O |
Voltage on I/O Pins |
0.5 to VDDQ +0.5 ( 4.6 V max.) |
V |
| VIN |
Voltage on Other Input Pins |
0.5 to VDD +0.5 ( 4.6 V max.) |
V |
| IIN |
Input Current on Any Pin |
+/20 |
mA |
| IOUT |
Output Current on Any I/O Pin |
+/20 |
mA |
| PD |
Package Power Dissipation |
1.5 |
W |
| TSTG |
Storage Temperature |
55 to 125 |
|
| TBIAS |
Temperature Under Bias |
55 to 125 |
|
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation hould be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
DescriptionThe GS8640E18/32/36T-xxxV is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the GS8640E18/32/36T-xxxV now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles of GS8640E18/32/36T-xxxV can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function of GS8640E18/32/36T-xxxV need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output GS8640E18/32/36T-xxxV register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT GS8640E18/32/36T-xxxV high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8640E18/32/36T-xxxV is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) GS8640E18/32/36T-xxxV is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8640E18/32/36T-xxxV operates on a 1.8 V or 2.5 V power supply. All inputs are 1.8 V or 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V or 2.5 V compatible.
GS8640E18 Data Sheet
