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GS840E36T

Features: •FT pin for user configurable flow through or pipelined operation.• Dual Cycle Deselect (DCD) Operation.• 3.3V +10%/-5% Core power supply• 2.5V or 3.3V I/O supply.•LBO pin for linear or interleaved burst mode.• Internal input resistors on mode pins all...

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SeekIC No. : 004356057 Detail

GS840E36T: Features: •FT pin for user configurable flow through or pipelined operation.• Dual Cycle Deselect (DCD) Operation.• 3.3V +10%/-5% Core power supply• 2.5V or 3.3V I/O supply.&...

GS840E36T Data Sheet

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Part Number:
GS840E36T
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/25

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Product Details

Description



Features:

• FT pin for user configurable flow through or pipelined operation.
• Dual Cycle Deselect (DCD) Operation.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or 119 Bump BGA package.


Application

The GS840E18/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version) high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU's, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS840E18/32/36 is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA package 




Pinout

Connection Diagram




Specifications

Symbol Description Value Unit
VDD Voltage on VDD Pins -0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins -0.5 to VDD V
VCK Voltage on Clock Input Pin -0.5 to 6 V
VI/O Voltage on I/O Pins -0.5 to VDDQ+0.5 ( 4.6 V max.) V
VIN Voltage on Other Input Pins -0.5 to VDD+0.5 ( 4.6 V max.) V
IIN Input Current on Any Pin +/- 20 mA
IOUT Output Current on Any I/O Pin +/- 20 mA
PD Package Power Dissipation 1.5 W
TSTG Storage Temperature -55 to 125
TBIAS Temperature Under Bias -55 to 125

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.


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