GS100

Features:

• 512K x 18 and 256K x 36 configurations
• User-configurable Pipelined and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
•  Read-Write-Read bus utilization
• Fully pin-compatible with both pipelined and flow through
   NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• ZQ mode pin for user selectable high /low output drive strength.
• x16/x32 mode with on-chip parity encoding and error detection
• Pin-compatible with 2M, 4M and 16M devices
• 3.3 V +10%/5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered, address, data, and control
• ZZ Pin for automatic power-down
• JEDEC-standard 119-Bump BGA  package   


Specifications

Parameter	Symbol	Min.	Typ.	Max.	Unit	Notes
Supply Voltage	VDD	3.135	3.3	3.6	V
I/O Supply Voltage	VDDQ	2.375	2.5	VDD	V	1
Input High Voltage	VIH	1.7	-	VDD +0.3	V	2
Input Low Voltage	VIL	0.3	-	0.8	V	2
Ambient Temperature (Commercial Range Versions)	TA	0	25	70	°C	3
Ambient Temperature (Industrial Range Versions)	TA	40	25	85	°C	3

Description

The GS882Z818/36B is an 8Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.

Because GS882Z818/36B is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO ) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. GS882Z818/36B feature eliminates complex off chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.