GLT5640AL16

Features:

• Single 3.3V ((±0.3V) power supply
• High speed clock cycle time -5.5:183MHz<3-3-3>,-6:166MHz<3-3-3>, -7:143MHz<3-3-3>,-8: 125MHz<3-3-3>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
•  X16  organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command 

Specifications

Parameter	Symbol	Conditions	Value	Unit
Supply Voltage	VDD	with respect to VSS	-0.5 to 4.6	V
Supply Voltage for Output	VDDQ	with respect to VSSQ	-0.5 to 4.6	V
Input Voltage	VI	with respect to VSS	-0.5 to VDD+0.5	V
Output Voltage	VO	with respect to VSSQ	-0.5 to VDDQ+0.5	V
Short circuit output current	IO		50	mA
Power dissipation	PD	Ta = 25 °C	1	W
Operating temperature	TOPT		0 to 70	°C
Storage temperature	TSTG		-65 to 150	°C

Description

The GLT5640AL16 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as
1,048,576 x 16 x 4 (word x bit x bank), respectively.

The synchronous DRAMs of GLT5640AL16 achieved high-speed data transfer using the pipeline architecture and clock frequency up
to 183MHz. All input and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are
compatible with Low Voltage TTL (LVTTL).GLT5640AL16 is packaged in 54-pin TSOPII.