GCDR3300A

The GCDR3300A is a macro to be used within the SH100G Gate Array-environment. This macro is designed for 2.5 - 3.3 GHz applications. GCDR3300A contains a 1:2 demultiplexer and a phase detector (PD) [1] with bit error detection and VCO (fig. 1).

The block named 'UP' and 'DOWN' represents a mixer circuit for the UP and DOWN signals of the PD  and the FD. The VCO GCDR3300A has its own GND (I9) and negative supply N2V5 (I10), and is controlled by pin I7 (VF0). With a frequency window detector (FD), an operational amplifier and a voltage reference diode, a complete PLL can be built. The external configuration of GCDR3300A is shown in figure 3.