Features: • 2.5 A, 500 V, RDS(on) = 2.5 @ VGS = 10 V• Low gate charge ( typical 10 nC )• Low Crss ( typical 8.5 pF)• Fast switching• 100 % avalanche tested• Improved dv/dt capabilitySpecifications Symbol Parameter FQD3N50C/FQU3N50C Units ...
FQU3N50C: Features: • 2.5 A, 500 V, RDS(on) = 2.5 @ VGS = 10 V• Low gate charge ( typical 10 nC )• Low Crss ( typical 8.5 pF)• Fast switching• 100 % avalanche tested• Impr...
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Symbol |
Parameter |
FQD3N50C/FQU3N50C |
Units | ||
VDSS |
Drain-Source Voltage |
500 |
V | ||
ID |
Drain Current |
- Continuous (TC =25°C) |
2.5 |
A | |
|
- Continuous (TC = 100°C) |
1.5 |
A | ||
IDM |
Drain Current Pulsed (Note 1) |
10 |
A | ||
VGSS |
Gate-Source Voltage |
± 30 |
V | ||
EAS |
Single Pulsed Avalanche Energy (Note 2) |
200 |
mJ | ||
IAR |
Avalanche Current (Note 1) |
2.5 |
A | ||
EAR |
Repetitive Avalanche Energy (Note 1) |
3.5 |
mJ | ||
d v/dt |
Peak Diode Recovery dv/dt (Note 3) |
4.5 |
V/ns | ||
PD |
Power Dissipation (TC = 25°C) |
35 |
W | ||
Operating and |
-55 to +150 |
°C | |||
TJ, TSTG |
Maximum lead temperature for soldering purposes, |
300 |
°C |
These P-Channel enhancement mode power field effect transistors of FQU3N50C are produced using Fairchild's proprietary, planar stripe, DMOS technology.
This advanced technology of FQU3N50C is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand a high energy pulse in the avalanche and commutation modes. FQU3N50C is well suited for electronic lamp ballasts based on the complementary half bridge topology.