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FM24C256

Features: • Extended Operating Voltages- C256: 4.5V - 5.5V- C256L: 2.7V - 5.5V- C256LZ: 2.7V - 5.5V• Low Power CMOS- 1mA active current typical- C256/C256L: 10µA standby current typical- C256LZ: less than 1µA standby current• 2-wire IIC serial interface• 64 byte...

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SeekIC No. : 004342238 Detail

FM24C256: Features: • Extended Operating Voltages- C256: 4.5V - 5.5V- C256L: 2.7V - 5.5V- C256LZ: 2.7V - 5.5V• Low Power CMOS- 1mA active current typical- C256/C256L: 10µA standby current ty...

FM24C256 Data Sheet

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Part Number:
FM24C256
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Extended Operating Voltages
- C256: 4.5V - 5.5V
- C256L: 2.7V - 5.5V
- C256LZ: 2.7V - 5.5V
• Low Power CMOS
- 1mA active current typical
- C256/C256L: 10µA standby current typical
- C256LZ: less than 1µA standby current
• 2-wire IIC serial interface
• 64 byte page write mode
• Max write cycle time of 6ms byte/page
• 40 years data retention
• Endurance: 100,000 data changes
• Hardware write protect for entire array
• Schmitt trigger inputs for noise suppression
• Electrostatic discharge protection > 4000V
• 8-pin DIP and 8-pin SO (150 mil) packages. Contact factory for CSP package availability


Pinout

Connection Diagram




Specifications

Ambient Storage Temperature ................65°C to +150°C
All Input or Output Voltages
with Respect to Ground ..................................6.5V to 0.3V
Lead Temperature
(Soldering,10 seconds) ............................................+300°C
ESD Rating ............................................................4000V min.


Description

The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS nonvolatile electrically erasable memory. FM24C256/C256L/C256LZ offer the designer different low voltage and low power options. They conform to all requirements in the Extended IIC 2-wire protocol.Furthermore, they are designed to minimize device pin count and simplify PC board layout requirements.

The entire memory of FM24C256/C256L/C256LZ array can be write disabled (Write Protection) by connecting the WP pin to VCC.

Functional address lines allow up to eight devices on the same bus, for up to a total of 2 Mbit address space.

The IIC communication protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).

Fairchild EEPROMs FM24C256/C256L/C256LZ are designed and tested for applications requiring high endurance, high reliability, and low power consumption.




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