FM24C17U

The FM24C16U/17U devices are 4096 bits of CMOS non-volatile electrically erasable memory. FM24C16U/17U  conform to all specifications in the Standard IIC 2-wire protocol. They are designed to minimize device pin count and simplify PC board layout requirements.

The upper half (upper 2Kbit) of the memory of the FM24C05U can be write protected by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS.

This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of EEPROM memory which is supported by the Fairchild family in 2K, 4K, 8K, and 16K FM24C16U/17U , allowing the user to configure the memory as the application requires with any combination of EEPROMs. In order to implement higher EEPROM memory densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the FM24C32 or FM24C65 datasheets for more information.) 

Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption.