FLEX 8000

`Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1)
2,500 to 16,000 usable gates
282 to 1,500 registers
`System-level features
In-circuit reconfigurability (ICR) via external Configuration EPROM or intelligent controller
Fully compliant with the peripheral component interconnect (PCI) standard
Built-in Joint-Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
MultiVolt^TM I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels
Low power consumption (typical specification less than 0.5 mA in standby mode)
`Flexible interconnect
FastTrack<sup>TM</sup> Interconnect continuous routing structure for fast, predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions)
Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions)
Tri-state emulation that implements internal tri-state nets
`Powerful I/O pins
Programmable output slew-rate control reduces switching noise
`Peripheral register for fast setup and clock-to-output delay
`Fabricated on an advanced SRAM process
`Available in a variety of packages with 84 to 304 pins (see Table 2)
`Software design support and automatic place-and-route provided by
the Altera®MAX+PLUS®II development system for 486- and Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations
`Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and Veribest

Altera's Flexible Logic Element MatriX (FLEX ® ) family combines the benefits of both erasable programmable logic devices (EPLDs) and fieldprogrammable gate arrays (FPGAs). The FLEX 8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs FLEX 8000 with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources.

FLEX 8000 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. FLEX 8000 are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers. The high-pin-count packages can integrate multiple 32-bit buses into a single device. Table 3 shows FLEX 8000 performance and LE requirements for typical applications.

All FLEX 8000 device packages provide four dedicated inputs for synchronous control signals with large fan-outs. Each I/O pin has an associated register on the periphery of the device. As outputs, these registers of FLEX 8000 provide fast clock-to-output times; as inputs, they offer quick setup times.

The logic and interconnections in the FLEX 8000 architecture are configured with CMOS SRAM elements. FLEX 8000 devices are configured at system power-up with data stored in an industry-standard parallel EPROM or an Altera serial Configuration EPROM device, or with data provided by a system controller. Altera offers the EPC1, EPC1213, EPC1064, and EPC1441 Configuration EPROMs, which configure FLEX 8000 devices via a serial data stream. Configuration data can also be stored in an industry-standard 32 K 8 bit or larger EPROM, or downloaded from system RAM. After a FLEX 8000 device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 100 ms, realtime changes can be made during system operation.